An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling-Reference-Cited by-同舟云学术

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An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

Published:2001-06 Issue:6 Volume:22 Page:287-289
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Diaz C.H.,Hun-Jan Tao ,Yao-Ching Ku ,Yen A.,Young K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/20008/00924844.pdf?arnumber=924844

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