Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/5466561/05466569.pdf?arnumber=5466569
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip;IET Circuits, Devices & Systems;2019-12-20
2. Addressing NoC Reliability Through an Efficient Fibonacci-Based Crosstalk Avoidance Codec Design;Algorithms and Architectures for Parallel Processing;2015
3. Error Correction Encoding for Tightly Coupled On-Chip Buses;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2014-12
4. Reliable Networks-on-Chip Design for Sustainable Computing Systems;Design Technologies for Green and Sustainable Computing Systems;2013
5. Dual-Layer Adaptive Error Control for Network-on-Chip Links;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-07
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