An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices-Reference-Cited by-同舟云学术

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices

Published:2023-07 Issue:7 Volume:70 Page:2645-2649
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Guo Zhiwang¹^ORCID,Chen Deyang¹,Zhao Chenyang¹^ORCID,Fang Jinbei¹,Jiang Jingwen¹,Liu Yixuan¹,Tian Haidong²,Xiong Xiankui²,Zhou Keji³^ORCID,Xue Xiaoyong¹^ORCID,Liu Qi³^ORCID,Zeng Xiaoyang¹

Affiliation:

1. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China

2. State Key Laboratory of Mobile Network and Mobile Communication Multimedia Technology, ZTE, Shenzhen, China

3. Frontier Institute of Chip and System, Fudan University, Shanghai, China

Funder

National Natural Science Foundation of China

Science and Technology Commission of Shanghai Municipality

Opening Project of Zhejiang Laboratory

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10164655/10026844.pdf?arnumber=10026844

Reference18 articles.

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4. CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays

5. A 14nm 100Kb 2T1R Transpose RRAM with150X resistance ratio enhancement and 27.% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme;wang;Proc Symp VLSI Technol,2021