A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend
Author:
Affiliation:
1. Department of Electronics Engineering, Hanyang University, Seoul, South Korea
2. Samsung Electronics, Hwaseong, South Korea
Funder
Samsung Electronics Company Ltd.
National Research Foundation of Korea
Korea Government
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10032206/09913680.pdf?arnumber=9913680
Reference8 articles.
1. A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth
2. A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
3. CMOS transceiver with baud rate clock recovery for optical interconnects
4. A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS
5. NRZ, Duobinary, or PAM4?: Choosing Among High-Speed Electrical Interconnects
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