Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits-Reference-Cited by-同舟云学术

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Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

Published:2014-04 Issue:4 Volume:61 Page:239-243
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kang-Sub Kwak ,Oh-Kyong Kwon

Funder

SKHynix Semiconductor Inc.

IC Design Education Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/6798683/06750722.pdf?arnumber=6750722

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-10

2. A 10-GHz Low-Power Serial Digital Majority Voter Based on Moving Accumulative Sign Filter in a PS-/PI-Based CDR;IEEE Transactions on Microwave Theory and Techniques;2020-12

3. A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop;IEICE Electronics Express;2020-10-25

4. Estimation of frequency and amplitude of ring oscillator built using current sources;Ain Shams Engineering Journal;2020-09

5. A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-11

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