Author:
Iparraguirre Daniel,Delgado-Frias Jose G.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
2 articles.
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1. A Network-on-Chip-Based Annealing Processing Architecture for Large-Scale Fully Connected Ising Model;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
2. ACHS Optimizations on 3D Interconnect Arrangements;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28