Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC

Author:

Yuan Fei1ORCID

Affiliation:

1. Department of Electrical, Computer, Biomedical Engineering, Toronto Metropolitan University, Toronto, Canada

Funder

Natural Science and Engineering Research Council (NSERC) of Canada

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14

4. Bi-Directional Gated Ring Oscillator Time Integrator;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09

5. A 3.97 µW 11.2b 500 kS/s Hybrid SAR ADC via Time-Mode Signal Processing;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

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