Configurable Image Rectification and Disparity Refinement for Stereo Vision-Reference-Cited by-同舟云学术

Configurable Image Rectification and Disparity Refinement for Stereo Vision

Published:2022-10 Issue:10 Volume:69 Page:3973-3977
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Dong Pingcheng¹^ORCID,Chen Zhuoyu¹^ORCID,Li Zhuoao¹^ORCID,Yao Ruoheng¹^ORCID,Zhang Wenyue¹,Zhang Yangyi¹,Chen Lei¹,Wang Chao²,An Fengwei³^ORCID

Affiliation:

1. School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

2. School of Optical and Electronic Information Education, Huazhong University of Science and Technology, Wuhan, China

3. School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China

Funder

Science, Technology, and Innovation Commission of Shenzhen Municipality

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9900496/09832005.pdf?arnumber=9832005

Reference17 articles.

1. A Real-Time High-Quality Complete System for Depth Image-Based Rendering on FPGA

2. FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization With Dynamic Clip-Threshold

3. A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices

4. A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Configurable Local-Expansion-Move Accelerator for Accurate Stereo Matching;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

2. Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-06

3. A Multi-scale Block PatchMatch-based Unified Algorithm for Efficient 6-D Vision Processing;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. Live Demonstration: A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Low-power Applications;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

5. A digital speckle stereo matching algorithm based on epipolar line correction;Signal, Image and Video Processing;2024-03-16