A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector-Reference-Cited by-同舟云学术

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A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Published:2019-03 Issue:3 Volume:66 Page:362-366
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kwon Dae-Hyun,Kim Minkyu^ORCID,Kim Sung-Geun,Choi Woo-Young^ORCID

Funder

Samsung

Ministry of Trade, Industry and Energy

Yonsei University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/8653436/08410680.pdf?arnumber=8410680

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 25-Gb/s PAM-4 Baud-rate CDR with High Jitter Tolerance using Shared Sampler Method;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2024-06-30

2. A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder;JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE;2023-10-31

3. A Sub-Sampling Phase Detector for Low-Power PAM4 Clock Recovery Circuit;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

4. Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-08

5. A software PAM4 clock data recovery algorithm for high‐speed serial communication;IET Communications;2022-02-09

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