A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control-Reference-Cited by-同舟云学术

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A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control

Published:2023 Issue: Volume: Page:1-1
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Yu Kai¹^ORCID,Yang Shangru²,Li Sizhen¹^ORCID,Huang Mo³^ORCID

Affiliation:

1. School of Integrated Circuits, Guangdong University of Technology, Guangzhou, China

2. School of Information Engineering, Guangdong University of Technology, Guangzhou, China

3. Department of Electrical and Computer Engineering (ECE), Institute of Microelectronics, State Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology (FST), University of Macau, Macao, China

Funder

National Key Research and Development Program of China

Science and Technology Development Fund, Macau SAR

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/4358609/10302323.pdf?arnumber=10302323

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