A 0.016mm<sup>2</sup> Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling-Reference-Cited by-同舟云学术

A 0.016mm² Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling

Published:2023-10 Issue:10 Volume:70 Page:3792-3796
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Zhong Junlin¹^ORCID,Yang Xiaofeng¹,Martins Rui P.²^ORCID,Zhu Yan¹^ORCID,Chan Chi-Hang¹^ORCID

Affiliation:

1. State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics University of Macau, Macau, China

2. Department of ECE/FST, State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, China

Funder

Ministry of Science and Technology of the People’s Republic of China

University of Macau

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10262390/10159125.pdf?arnumber=10159125

Reference16 articles.

1. Self-Coupling and Mutual Pulling in Phase-Locked Loops

2. 17.3 A ?58dBc-worst-fractional-spur and- 234dB-FoM jitter, 5.5 GHz ring-DCO-based fractional-N DPLL using a time-invariant-probability modulator, generating a nonlinearity-robust DTC-control word;seong;Proc IEEE Int Solid-State Circuits Conf,2020

3. A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction

4. A 1.6-to-3.0-GHz Fractional-${N}$ MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power

5. A 2.4-GHz RF Fractional- ${N}$ Synthesizer With BW $= 0.25f_{\mathrm{ REF}}$