A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator-Reference-Cited by-同舟云学术

A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator

Published:2023-04 Issue:4 Volume:70 Page:1366-1370
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Lin Yudeng¹^ORCID,Tang Jianshi²^ORCID,Gao Bin²^ORCID,Qin Qi¹^ORCID,Zhang Qingtian²^ORCID,Qian He²,Wu Huaqiang²^ORCID

Affiliation:

1. School of Integrated Circuits, Beijing Innovation Center for Future Chips (ICFC), Tsinghua University, Beijing, China

2. School of Integrated Circuits, Beijing Innovation Center for Future Chips and the Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China

Funder

Ministry of Science and Technology (MOST) of China

National Natural Science Foundation of China

XPLORER Prize

Beijing Advanced Innovation Center for Integrated Circuits

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10083009/09963663.pdf?arnumber=9963663

Reference21 articles.

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4. A survey on Bayesian deep learning;wang;arXiv 1604 01662,2016

5. Characterizing Endurance Degradation of Incremental Switching in Analog RRAM for Neuromorphic Systems

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