A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing
Author:
Affiliation:
1. State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China
Funder
National Natural Science Foundation of China
University of Macau Research
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/8920/10537170/10472602.pdf?arnumber=10472602
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1. COVID-Net: a tailored deep convolutional neural network design for detection of COVID-19 cases from chest X-ray images
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3. Dual-Branch Squeeze-Fusion-Excitation Module for Cross-Modality Registration of Cardiac SPECT and CT
4. A Survey of Convolutional Neural Networks: Analysis, Applications, and Prospects
5. ONCE-3DLanes: Building Monocular 3D Lane Detection
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