An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation
Author:
Affiliation:
1. Texas Analog Center of Excellence and the Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX, USA
2. Texas Analog Center of Excellence, University of Texas at Dallas, Richardson, TX, USA
Funder
Semiconductor Research Corporation (SRC) through Texas Analog Center of Excellence at the University of Texas at Dallas
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9969381/09803213.pdf?arnumber=9803213
Reference13 articles.
1. A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction;setterberg;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2013
2. Low-power low-voltage analog-to-digital conversion techniques using pipelined architectures;cho,1995
3. An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS
4. A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS
5. 3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
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