Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology-Reference-Cited by-同舟云学术

Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology

Published:2023-09 Issue:9 Volume:70 Page:3639-3643
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Widmer Sandro¹,Kossel Marcel¹^ORCID,Cherubini Giovanni¹,Woźniak Stanislaw¹^ORCID,Francese Pier Andrea¹^ORCID,Stanojevic Ana¹^ORCID,Brändli Matthias¹^ORCID,Frick Klaus²,Pantazi Angeliki¹^ORCID

Affiliation:

1. Hybrid Cloud Research, IBM Research GmbH, Rüschlikon, Switzerland

2. ICE Institut für Computional Engineering, OST-Eastern Switzerland University of Applied Sciences, St. Gallen, Switzerland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10235305/10129114.pdf?arnumber=10129114

Reference10 articles.

1. Spiking Neural Networks Hardware Implementations and Challenges

2. Approximating Relu Networks by Single-Spike Computation

3. A Neuromorphic VLSI Circuit for Spike-Based Random Sampling

4. Supervised learning based on temporal coding in spiking neural networks;mostafa;IEEE Trans Neural Netw Learn Syst,2018

5. First spikes in ensembles of human tactile afferents code complex spatial fingertip events

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