Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/8920/6476647/06412783.pdf?arnumber=6412783
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3. Design of clock and data recovery system’s behavioral model for high speed transceivers of serial interfaces;ITM Web of Conferences;2019
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