Low Consumption Balanced Front-End Amplifiers Robust to Load Variations in 65nm PD-SOI CMOS Technology for 60 GHz Short-Range Wireless Applications
Author:
Affiliation:
1. University of Bordeaux, IMS Research Laboratory, CNRS, UMR 5218, 3405, Talence, France
2. Bordeaux INP, IMS Research Laboratory, CNRS, UMR 5218, Talence, France
3. STMicroelectronics, Hardware Design Center (HDC), Crolles, France
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9900496/09803267.pdf?arnumber=9803267
Reference14 articles.
1. Design of 60-GHz 90-nm CMOS balanced power amplifier with miniaturized quadrature hybrids
2. Design of an Ultra-Compact 60-GHz Bi-Directional Amplifier in 65-nm CMOS
3. A 28 GHz and 38 GHz High-Gain Dual-Band Power Amplifier for 5G Wireless Systems in 22 nm FD-SOI CMOS
4. 5 GHz low-power RTD-based amplifier MMIC with a high figure-of-merit of 24.5 dB/mW
5. Efficient 60-GHz Power Amplifier With Adaptive AM-AM and AM-PM Distortions Compensation in 65-nm CMOS Process
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1. A 60-GHz Variable-Gain Power Amplifier With a Switchable Inductor for TDD Systems;IEEE Microwave and Wireless Technology Letters;2024-05
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