A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization
Author:
Funder
Singapore Ministry of Education
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9524868/09446608.pdf?arnumber=9446608
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A nA-Range Area-Efficient Sub-100-ppm/$^\circ$C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI;IEEE Journal of Solid-State Circuits;2024
2. A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05
3. A 79 pW, 106 ppm/°C NMOS-only current reference with leakage current isolation based on body bias technique;AEU - International Journal of Electronics and Communications;2023-03
4. An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation;AEU - International Journal of Electronics and Communications;2023-03
5. Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V;IEEE Access;2023
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