Low Power Ripple Carry Adder Using Hybrid 1-Bit Full Adder Circuit-Reference-Cited by-同舟云学术

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Low Power Ripple Carry Adder Using Hybrid 1-Bit Full Adder Circuit

Published:2019-01 Issue: Volume: Page:
ISSN:
Container-title:2019 11th International Conference on Computational Intelligence and Communication Networks (CICN)
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Author:

BAGWARI ASHISH,KATNA ISHA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8896806/8902350/08902351.pdf?arnumber=8902351

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

2. Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

3. A Novel 1-bit Fast and Low Power 19-T Full Adder Circuit at 45 nm Technology Node;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

4. Designing Carry Look Ahead Adder to Enrich Performance using One Bit Hybrid Full Adder;2022 International Conference on Electronics and Renewable Systems (ICEARS);2022-03-16

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