ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4556699/4556700/04556726.pdf?arnumber=4556726
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Understanding object-level memory access patterns across the spectrum;Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis;2017-11-12
2. An efficient trade-off between yield and energy for eDRAM caches under process variations;Microprocessors and Microsystems;2017-11
3. Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation;Circuits, Systems, and Signal Processing;2017-03-11
4. Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-07
5. Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-07
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