A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8355238/8357004/08357009.pdf?arnumber=8357009
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link;IEEE Access;2023
2. A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS;2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2022-11-11
3. A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems;IEEE Journal of Solid-State Circuits;2022-05
4. A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE;IEICE Electronics Express;2021-09-10
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