Author:
Liu Yuanzhuo,Bai Siqi,Pu Bo,Xu Zhifei,Chen Bichen,Venkataraman Srinivas,Wang Xu,Fan Jun,Kim DongHyun
Funder
National Science Foundation
Cited by
2 articles.
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1. Closed-Loop Structure for Mitigating Jitter-Induced Noise of Clock Source in High-Bandwidth Signal Sampling;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20
2. A Method to Reduce Jitter Due to Power Noise by Optimizing Loop Filter in PLL Based Clock Source;2022 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC);2022-09-01