Author:
Fiser Petr,Halecek Ivo,Schmidt Jan
Cited by
7 articles.
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1. Delay-aware evolutionary optimization of digital circuits;2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2022-07
2. Resynthesis of logic circuits using machine learning and reconvergent paths;2021 24th Euromicro Conference on Digital System Design (DSD);2021-09
3. Revisiting Explicit Enumeration for Exact Synthesis;2020 23rd Euromicro Conference on Digital System Design (DSD);2020-08
4. SAT-Sweeping Enhanced for Logic Synthesis;2020 57th ACM/IEEE Design Automation Conference (DAC);2020-07
5. SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support;Journal of Circuits, Systems and Computers;2019-12-01