A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers

Author:

Paim GuilhermeORCID,Amrouch HussamORCID,Rocha Leandro M. G.ORCID,Abreu BrunnoORCID,Cesar da Costa Eduardo Antonio,Bampi SergioORCID,Henkel JorgORCID

Funder

Deutsche Forschungsgemeinschaft

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Understanding Timing Error Characteristics from Overclocked Systolic Multiply–Accumulate Arrays in FPGAs;Journal of Low Power Electronics and Applications;2024-01-09

2. Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm;2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W);2023-06

3. Impact of the Noise on the Emulated Grid Voltage Signal in Hardware-in-the-Loop Used in Power Converters;Electronics;2023-02-04

4. Read-Write Dependency Aware Register Allocation;Computer Systems Science and Engineering;2023

5. A Multiplier-Less Level-3 Haar Wavelet Transform Approximation Requiring Five Additions Only;2022 IEEE 15th Dallas Circuit And System Conference (DCAS);2022-06-17

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