Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop-Reference-Cited by-同舟云学术

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Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop

Published:2021 Issue: Volume: Page:1-1
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Lin Dave Y.-W.¹,Wen Charles H.-P.²

Affiliation:

1. Electrical and Computer Engineering, National Chiao Tung University, 34914 Hsinchu, Hsinchu, Taiwan, 300 (e-mail: linyeuwen0112.eed04g@g2.nctu.edu.tw)

2. Electrical and Computer Engineering, National Chiao Tung University, 34914 Hsinchu, Hsinchu, Taiwan, (e-mail: opwen@g2.nctu.edu.tw)

Funder

Ministry of Science and Technology Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/4358213/09392324.pdf?arnumber=9392324

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Investigative Study on Performance and Reliability Effects on S2C/TSPC/SCD D-Flip-Flops using 16 nm CMOS Process;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14

2. General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme;Journal of Electronic Testing;2024-01-09

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