Modified High Speed 32-bit Vedic Multiplier Design and Implementation

Author:

Murugesh M. Bala,Nagaraj S.,Jayasree J.,Reddy G. Vijay Kumar

Publisher

IEEE

Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. 16-bit Vedic multiplier Using Carry Skip Adder;2024 International Conference on Intelligent Systems for Cybersecurity (ISCS);2024-05-03

2. Performance Analysis of Vedic Multiplier in Hardware Implementation of Biomedical Applications;International Journal of Innovative Science and Research Technology (IJISRT);2024-04-04

3. Performance Analysis of Vedic Multiplier in Signal Processing Applications;International Journal of Innovative Science and Research Technology (IJISRT);2024-04-03

4. Design and Implementation of 8-Bit Vedic Multiplier Using Cadence 45nm Technology;2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2024-01-11

5. Design of an Efficient Mac Unit for DSP Applications;2023 Intelligent Computing and Control for Engineering and Business Systems (ICCEBS);2023-12-14

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