Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes
Author:
Affiliation:
1. Department of Computer Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/6287639/10380310/10439174.pdf?arnumber=10439174
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