A Novel Multiplier-Less LMS Adaptive Filter Design Based on Offset Binary Coded Distributed Arithmetic
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science
Link
http://xplorestaging.ieee.org/ielx7/6287639/9312710/09439956.pdf?arnumber=9439956
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Optimized VLSI Implementation of the Least Mean Square (LMS) Adaptive Filter Architecture on the Basis of Distributed Arithmetic Approach;Journal of The Institution of Engineers (India): Series B;2024-03-15
2. FPGA design and implementation of an efficient FIR adaptive filter by adopting CSD based approximate distributed arithmetic architecture;International Journal of Mobile Communications;2024
3. Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09
4. High-Performance and Energy-Efficient FIR Filter Architecture Using Parallel Prefix Adder-Based Triangular Common Subexpression Elimination Algorithm for IoT Enabled Wireless Sensor Network;2023 3rd Asian Conference on Innovation in Technology (ASIANCON);2023-08-25
5. Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders;Circuits, Systems, and Signal Processing;2023-07-21
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