Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm-Reference-Cited by-同舟云学术

Test Scheduling and Test Time Minimization of System-on-Chip Using Modified BAT Algorithm

Author:

Chandrasekaran Gokul¹^ORCID,Kumar Neelam Sanjeev²,Karthikeyan P. R.³^ORCID,Vanchinathan K.¹,Priyadarshi Neeraj⁴^ORCID,Twala Bhekisipho⁵^ORCID

Affiliation:

1. Department of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Erode, India

2. Department of Biomedical Engineering, Saveetha School of Engineering, SIMATS, Chennai, India

3. Department of Electronics and Communication Engineering, Saveetha School of Engineering, SIMATS, Chennai, India

4. Department of Electrical Engineering, JIS College of Engineering, Kolkata, India

5. Digital Transformation Portfolio, Tshwane University of Technology, Pretoria, South Africa

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

Reference52 articles.

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