A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration-Reference-Cited by-同舟云学术

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

Published:2021 Issue: Volume:9 Page:133143-133155
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Verma Deeksha^ORCID,Rikan Behnam S.^ORCID,Shehzad Khuram^ORCID,Kim Sung Jin^ORCID,Khan Danial^ORCID,Kommangunta Venkatesh,Shah Syed Adil Ali,Pu Younggun^ORCID,Yoo Sang-Sun^ORCID,Hwang Keum Cheol^ORCID,Yang Youngoo^ORCID,Lee Kang-Yoon^ORCID

Funder

Korea Government (MOTIE)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/9312710/09548087.pdf?arnumber=9548087

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