1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications-Reference-Cited by-同舟云学术

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1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

Published:2016 Issue: Volume:4 Page:5452-5473
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Li An,Hailes Peter,Maunder Robert G.,Al-Hashimi Bashir M.,Hanzo Lajos^ORCID

Funder

EPSRC, Swindon, U.K.

TSB, Swindon, U.K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/7419931/07539551.pdf?arnumber=7539551

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