A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices-Reference-Cited by-同舟云学术

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A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices

Published:2020 Issue: Volume:8 Page:162491-162506
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Lim Seung-Ho^ORCID,Lee Jae-Bin,Kim Geon-Myeong,Ahn Woo Hyun^ORCID

Funder

National Research Foundation of Korea (NRF) grant

Korea government [Ministry of Science and ICT (MSIT)]

Hankuk University of Foreign Studies Research Fund, and the Research Grant of Kwangwoon University in 2020

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

Link

http://xplorestaging.ieee.org/ielx7/6287639/8948470/09186119.pdf?arnumber=9186119

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An FPGA-based QC-LDPC encoder design;2024 5th International Conference on Computer Engineering and Application (ICCEA);2024-04-12

2. Efficient Constrained Codes That Enable Page Separation in Modern Flash Memories;IEEE Transactions on Communications;2023-12

3. A Novel Channel Coding Scheme by Concatenating LDPC with BCH for NAND Flash Memory;Journal of Physics: Conference Series;2022-06-01

4. Laser Communication Test System Based on Ten Gigabit Ethernet;2021 IEEE 15th International Conference on Electronic Measurement & Instruments (ICEMI);2021-10-29

5. Photoinduced-reset and multilevel storage transistor memories based on antimony-doped tin oxide nanoparticles floating gate;Nanotechnology;2021-10-22

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