Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques-Reference-Cited by-同舟云学术

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

Published:2023 Issue: Volume:11 Page:34942-34951
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Moon Byeong-Taek¹^ORCID,Yun Byeonghun¹^ORCID,Kim Jusung²^ORCID,Lee Sang-Gug¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea

2. Department of Electronics Engineering, Hanbat National University, Daejeon, South Korea

Funder

Institute of Information & Communications Technology Planning & Evaluation (IITP) funded by the Korean Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10092735.pdf?arnumber=10092735

Reference31 articles.

1. A 99 - 132 GHz Frequency Quadrupler with 8.5 dBm Peak Output Power and 8.8% DC-to-RF Efficiency in 130 nm BiCMOS

2. A 9% power efficiency 121-to-137 GHz phase-controlled push-push frequency quadrupler in 0.13 ?m SiGe BiCMOS;wang;Proc IEEE Int Solid-State Circuits Conf,2012

3. A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87 % Power Efficiency Based on Harmonic Matched $G_{\max}$-Core

4. Frequency Multiplication With Adjustable Waveform Shaping Demonstrated at 200 GHz

5. 160–310 GHz frequency doubler in 65-nm CMOS with 3-dBm peak output power for rotational spectroscopy

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