Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

Author:

Mohamed Karimeldeen1ORCID,Yasseen Khaled Y.2,Murmann Boris3ORCID,Omran Hesham2ORCID

Affiliation:

1. Department of Electrical Engineering, Suez Canal University, Ismailia, Egypt

2. Integrated Circuits Laboratory (ICL), Faculty of Engineering, Ain Shams University, Cairo, Egypt

3. Department of Electrical Engineering, Stanford University, Stanford, CA, USA

Funder

Egypt’s Information Technology Industry Development Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Two gm/ID design approaches for high-performance dual-resistive feedback noise-cancelling LNA;International Journal of Electronics;2024-07-28

2. gm/ID methodology applied to ring oscillators;Integration;2024-07

3. A Complete Automated Analog Flow from Design Generation to Post-layout Verification;2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2023-12-18

4. Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model;2023 7th International Young Engineers Forum (YEF-ECE);2023-07-07

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