A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET
Author:
Affiliation:
1. Texas A&M University,College Station,TX,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772785.pdf?arnumber=9772785
Reference7 articles.
1. A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS
2. A 31.5-GHz BW 6.4-b ENOB 56-GS/s ADC in 28nm CMOS for 224-Gb/s DP-16QAM coherent receivers
3. 6.3 A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET
4. A background calibrated 28GS/s 8b interleaved SARADC in 28nm CMOS;le;CICC,2017
5. A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET;frans;VLSI,2016
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2. A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS;IEEE Journal of Solid-State Circuits;2024-03
3. 22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
4. A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
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