A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process-Reference-Cited by-同舟云学术

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process

Published:2022-04 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Kim Joohwan¹,Park Junyoung¹,Byun Jindo¹,Seol Changkyu¹,Soo Yoon Chang¹,Shin EunSeok¹,Cho Hyunyoon¹,Um Youngdo¹,Lee Sucheol¹,Jin Hyungmin¹,Shin Kwangseob¹,Rie Hyunsub Norbert¹,Jung Minsu¹,Park Jin-Hee¹,Cha Go-Eun¹,Lee Minjae¹,Kim YoungMin¹,Han Byeori¹,Jeon Yuseong¹,Lee Jisun¹,So Hyejeong¹,Kim Sungduk¹,Park Wansoo¹,Kim Tae young¹,Choi Youngdon¹,Choi Jung-Hwan¹,Ko Hyungjong¹,Lee Sang-Hyun¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772814.pdf?arnumber=9772814

Reference4 articles.

1. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2. A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS;xuqiang;2017 IEEE Custom Integrated Circuits Conference (CICC),0

3. 6.5 A 1.8 pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS;dickson;2017 IEEE International Solid-State Circuits Conference (ISSCC),0

4. An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling;hollis;IEEE Journal of Solid-State Circuits,2021

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1. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01