Author:
Beest F.T.,Peeters A.,Verra M.,van Berkel K.,Kerkhoff H.
Cited by
12 articles.
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1. Scan and Automated Test Pattern Generation in VLSI;2024 5th International Conference on Image Processing and Capsule Networks (ICIPCN);2024-07-03
2. Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits;Journal of Electronic Testing;2021-08
3. At-speed DfT Architecture for Bundled-data Design;2020 IEEE International Test Conference (ITC);2020-11-01
4. DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-01
5. Test Methodology for Dual-rail Asynchronous Circuits;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18