A novel architecture for on-chip path delay measurement
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5348788/5355529/05355742.pdf?arnumber=5355742
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Performance Screening Using Functional Path Ring Oscillators;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-06
2. A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data;2022 IEEE International Test Conference (ITC);2022-09
3. Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators;2022 IEEE European Test Symposium (ETS);2022-05-23
4. Time-Dependent Degradation in Device Characteristics and Countermeasures by Design;VLSI Design and Test for Systems Dependability;2018-07-21
5. Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017
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