An Improved Systolic Architecture for LU Decomposition
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4019472/4019473/04019521.pdf?arnumber=4019521
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-04
3. Sign-Select Lookahead CORDIC based High-Speed QR Decomposition Architecture for MIMO Receiver Applications;JSTS:Journal of Semiconductor Technology and Science;2011-03-31
4. A Unified Co-Processor Architecture for Matrix Decomposition;Journal of Computer Science and Technology;2010-07
5. A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs;2009 17th IEEE Symposium on Field Programmable Custom Computing Machines;2009
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