Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype-Reference-Cited by-同舟云学术

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Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation, and Validation of a PMU Prototype

Published:2014-12 Issue:12 Volume:63 Page:2824-2836
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Romano Paolo,Paolone Mario

Funder

European Community’s Seventh Framework Programme FP7-ICT-2011-8 through C-DAX

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/6940066/06818415.pdf?arnumber=6818415

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