Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module-Reference-Cited by-同舟云学术

Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module

Published:2022-12-12 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
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Author:

Kim Hyunwoo¹,Kim Haeyeon¹,Park Joonsang¹,Son Keeyoung¹,Park Hyunwook¹,Shin Taein¹,Kim Keunwoo¹,Yoon Jiwon¹,Lee Junghyun¹,Hong Jonghyun¹,Kim Juneyoung¹,Kim Joungho¹

Affiliation:

1. Korea Advanced Institute of Science and Technology (KAIST),Terabyte Interconnection and Package Laboratory,Daejeon,Republic of Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9994795/9994852/09995183.pdf?arnumber=9995183

Reference7 articles.

1. PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models;pak;IEEE Transactions on Components Packaging and Manufacturing Technology,2011

2. The Transmission-Line Modeling (TLM) Method in Electromagnetics

3. Power Delivery for Silicon Interconnect Fabric

4. High-Frequency Modeling and Signal Integrity Analysis of a Silicone Rubber Socket for High-Performance Package

5. Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs

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1. Modeling and Analysis of Simultaneous Switching Noise for Full Wafer Scale Chip Core;2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS);2023-10-15