A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter 0.25-μm CMOS

Author:

Benyong Zhang ,Allen P.E.,Huard J.M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 0.9-V 6400-μm2 Resistor-Based Temperature Sensor With a One-Point Trimmed 3σ Inaccuracy of ±0.64 °C from −50°C to 125 °C;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-09

2. A PLL Frequency Synthesizer Design for C-band Satellite Communications;2023 10th International Conference on Recent Advances in Air and Space Technologies (RAST);2023-06-07

3. Design of a Configurable Third-Order Gm-C Filter Using QFG and BD-QFG MOS-Based OTA for Fast Locking Speed PLL;Journal of Circuits, Systems and Computers;2022-09-14

4. Reference Spur Reduction in Sampled-loop filter PLLs by Oversampling;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

5. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-09

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