40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-$\mu{\hbox {m}}$ CMOS-Reference-Cited by-同舟云学术

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40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-$\mu{\hbox {m}}$ CMOS

Published:2007-12 Issue:12 Volume:42 Page:2715-2725
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chien Jun-Chau,Lu Liang-Hung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4381435/04381440.pdf?arnumber=4381440

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2. Loss-Compensated Cascaded Multistage Distributed Power Amplifier in 65nm CMOS Technology;IEEE Access;2024

3. Design and Analysis of Active Feedback RGC-based Transimpedance Receiver Circuit for Optical Interconnects;Journal of Circuits, Systems and Computers;2023-11-11

4. Evolution of Broadband Amplifier Design: From Single-Stage to Distributed Topology;IEEE Microwave Magazine;2023-09

5. Fully Integrated Efficient and Wideband Distributed Amplifier Employing Dual-Feed Output Stage With Active Input Split-Stage in 0.13μm CMOS;IEEE Access;2023

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