The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx5/4/32000/01487620.pdf?arnumber=1487620
Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device;Journal of Electrical Engineering & Technology;2021-03-09
2. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process;Nanoscale Research Letters;2020-11-11
3. High Trigger Current NPN Transistor With Excellent Double-Snapback Performance for High-Voltage Output ESD Protection;IEEE Electron Device Letters;2020-03
4. Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering;Electronics;2019-12-03
5. Novel Silicon-Controlled Rectifier With Snapback-Free Performance for High-Voltage and Robust ESD Protection;IEEE Electron Device Letters;2019-03
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