Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access-Reference-Cited by-同舟云学术

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Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

Published:2009-03 Issue:3 Volume:44 Page:977-986
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nii Koji,Tsukamoto Yasumasa,Yabuuchi Makoto,Masuda Yasuhiro,Imaoka Susumu,Usui Keiichi,Ohbayashi Shigeki,Makino Hiroshi,Shinohara Hirofumi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4787550/04787570.pdf?arnumber=4787570

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism;Journal of Low Power Electronics and Applications;2024-01-04

2. Implementation and Performance Evaluation of Hybrid SRAM Architectures Using 6T and 7T for Low-Power Applications;Communication, Software and Networks;2022-10-28

3. Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing;IEEE Journal of Solid-State Circuits;2022

4. The Stability Performance Analysis of SRAM Cell Topologies in 90nm and 130nm CMOS technology;2021 International Conference on Emerging Smart Computing and Informatics (ESCI);2021-03-05

5. Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros;IEEE Access;2021

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