An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion-Reference-Cited by-同舟云学术

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Published:2008-01 Issue:1 Volume:43 Page:121-131
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bae Seung-Jun,Park Kwang-Il,Ihm Jeong-Don,Song Ho-Young,Lee Woo-Jin,Kim Hyun-Jin,Kim Kyoung-Ho,Park Yoon-Sik,Park Min-Sang,Lee Hong-Kyong,Bang Sam-Young,Moon Gil-Shin,Hwang Seok-Won,Cho Young-Chul,Hwang Sang-Jun,Kim Dae-Hyun,Lim Ji-Hoon,Kim Jae-Sung,Kim Sung-Hoon,Jang Seong-Jin,Choi Joo Sun,Jun Young-Hyun,Kim Kinam,Cho Soo-In

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4443178/04443181.pdf?arnumber=4443181

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