A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS-Reference-Cited by-同舟云学术

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A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS

Published:2009-12 Issue:12 Volume:44 Page:3344-3358
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Park Matthew,Perrott Michael H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5342337/05342354.pdf?arnumber=5342354

Cited by 125 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mixed-Order Correlated Dual-Loop Sturdy MASH CT-$\Delta \Sigma $ Modulator With Distributed Signal Feed-In and VCO Quantizer;IEEE Journal of Solid-State Circuits;2024

2. A Closed-Loop VCO-based 1-1 SMASH CT ΔΣ ADC Architecture;Journal of Physics: Conference Series;2023-10-01

3. A Time-Domain Readout Technique for Neural Interfaces Based on VCO-Timestamping;IEEE Transactions on Biomedical Circuits and Systems;2023-06

4. A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21

5. A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03

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