Author:
Satheesan Abin,Geethiga S
Cited by
3 articles.
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1. Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates;2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S);2024-06-08
2. Design and Performance Analysis of an Asynchronous 16×2 DRAM Architecture Using 2T1C DRAM Bitcell and 70.15 µW GDI Based 2 to 4 Decoder;2024 6th International Conference on Electrical Engineering and Information & Communication Technology (ICEEICT);2024-05-02
3. Implementation of Power Efficient Radix-4 Booth Multiplier with Pre-encoding;2023 7th International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS);2023-11-02