A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9146894/9162771/09162787.pdf?arnumber=9162787
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Energy Efficient and Temperature Stable Digital FLL-Based Wakeup Timer With Time-Domain Temperature Compensation;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. A 1.2V, 0.25%/V, 50ppm/°C, 1% Precision, 500kHz Relaxation Oscillator in 55nm CMOS;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09
3. A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier;IEEE Journal of Solid-State Circuits;2023-10
4. A Process-Scalable Ultra-Low-Voltage 180kHz Sleep Timer with a Time-Domain Amplifier and a Switch-less Resistance Multiplier;2022 IEEE Asian Solid-State Circuits Conference (A-SSCC);2022-11-06
5. A Radiation-Hardened Frequency–Locked Loop On–Chip Oscillator with 33.6ppm/°C Stability for Space Applications;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
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