Area-Time Efficient of 2-D DWT using Modified DA Technique and Reversible Gate
Author:
Affiliation:
1. Technocrats Institute of Technology,Department of Electronics and Communication Engineering,Bhopal
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9971791/9971808/09972239.pdf?arnumber=9972239
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1. LDPC check node implementation using reversible logic
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4. Design and VLSI Implementation of CSD based DA Architecture for 5/3 DWT;gardezi;Proceedings of 6th International Bhurban Conference on Applied Sciences and Technology (IBCAST),0
5. Reversible full/half adder with optimum power dissipation
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